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documentation:microcontroleurs:stm32:stm32f030f4p6:index [2018/08/27 22:07] – f1sls | documentation:microcontroleurs:stm32:stm32f030f4p6:index [2018/08/27 22:48] (Version actuelle) – f1sls | ||
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====== STM32F030F4P6 ====== | ====== STM32F030F4P6 ====== | ||
+ | |||
+ | * [[https:// | ||
* Core: ARM®32-bit Cortex®-M0 CPU, frequency up to 48 MHz | * Core: ARM®32-bit Cortex®-M0 CPU, frequency up to 48 MHz | ||
* Memories | * Memories | ||
Ligne 7: | Ligne 9: | ||
* CRC calculation unit | * CRC calculation unit | ||
* Reset and power management | * Reset and power management | ||
- | | + | |
- | * Analog supply: VDDA= VDDto 3.6 V | + | * Analog supply: VDDA= VDDto 3.6 V |
- | * Power-on/ | + | * Power-on/ |
- | * Low power modes: Sleep, Stop, Standby | + | * Low power modes: Sleep, Stop, Standby |
* Clock management | * Clock management | ||
- | | + | |
- | * 32 kHz oscillator for RTC with calibration | + | * 32 kHz oscillator for RTC with calibration |
- | * Internal 8 MHz RC with x6 PLL option | + | * Internal 8 MHz RC with x6 PLL option |
- | * Internal 40 kHz RC oscillator | + | * Internal 40 kHz RC oscillator |
* Up to 55 fast I/Os | * Up to 55 fast I/Os | ||
- | | + | |
- | * Up to 55 I/Os with 5V tolerant capability | + | * Up to 55 I/Os with 5V tolerant capability |
* 5-channel DMA controller | * 5-channel DMA controller | ||
* One 12-bit, 1.0 μs ADC (up to 16 channels) | * One 12-bit, 1.0 μs ADC (up to 16 channels) | ||
- | | + | |
- | * Separate analog supply: 2.4 V to 3.6 V | + | * Separate analog supply: 2.4 V to 3.6 V |
* Calendar RTC with alarm and periodic wakeup from Stop/ | * Calendar RTC with alarm and periodic wakeup from Stop/ | ||
* 11 timers | * 11 timers | ||
- | | + | |
- | * Up to seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding | + | * Up to seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding |
- | * Independent and system watchdog timers | + | * Independent and system watchdog timers |
- | * SysTick timer | + | * SysTick timer |
* Communication interfaces | * Communication interfaces | ||
- | | + | |
- | * Up to six USARTs supporting master synchronous SPI and modem control; one with auto baud rate detection | + | * Up to six USARTs supporting master synchronous SPI and modem control; one with auto baud rate detection |
- | * Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames | + | * Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames |
- | * Serial wire debug (SWD) | + | * Serial wire debug (SWD) |
* All packages ECOPACK®2 | * All packages ECOPACK®2 | ||
- | ===== Datasheet | + | ===== Documents |
- | {{ : | + | |
+ | * {{ : | ||
+ | |||
+ | |||
+ | ---- | ||
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+ | {{: | ||
+ | {{: | ||
+ | {{: |